• 专利附录
  • 专利说明
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    • 专利摘要:
    The present invention discloses a first-in first-out memory and a flag generation method of the memory. The memory includes a write address generation circuit for generating a write address in response to the write clock signal, a read address generation circuit for generating the read address in response to the read clock signal, a plurality of write and read word lines and a plurality of writes; A memory cell array having a plurality of memory cells between each of the read bit lines, storing write data in response to a write address, and outputting read data in response to the read address; Comparing the read address, if the same, the full flag signal is generated in response to the write clock signal.If the read address is the same, the flag signal for generating the empty flag signal is generated in response to the read clock signal. Circuit have. Therefore, since the flag signal is generated at a high speed, it is easy to apply to a high speed system.
    公开号:KR20020052669A
    申请号:KR1020000082094
    申请日:2000-12-26
    公开日:2002-07-04
    发明作者:이영주；임정주
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    First-in, first-out memory and flag signal generating method
    [17] The present invention relates to a semiconductor memory device, and more particularly, to a first input first output (FIFO) memory that reads first written data first.
    [18] In general, in communications between processors (or systems) with different data rates, the speed at which one processor (or system) writes data is different from the rate at which another processor (or system) reads the data. There is a difference between the speeds. Thus, a first-in first-out memory is provided between processors having different data rates to control data transfer between the processors.
    [19] Fig. 1 is a block diagram showing data transfer between conventional processors, and is comprised of processors 10, 12, and first-in, first-out memory 14.
    [20] In Fig. 1, the processor 10 transmits input data IN to the first-in, first-out memory 14, and the processor 12 transmits the data transmitted from the first-in, first-out memory 14 to the output data OUT. The data transfer rate of the processor 10 is faster than the data transfer rate of the processor 12.
    [21] The first-in first-out memory 14 is reset in response to a reset signal reset from the processor 10, is enabled in response to the write enable signal WEB transmitted from the processor 10, and the write clock signal WCK. The write data WD in response to the " At this time, if the first-in first-out memory 14 is full, the full flag signal Full is transmitted to the processor 10 to prevent the processor 10 from writing data. The read data RD is enabled in response to the read enable signal REB transmitted from the processor 12, and the read data RD is transmitted to the processor 12 in response to the read clock signal RCK. At this time, if the first-in first-out memory 14 is empty, the empty flag signal (Empty) is transmitted to the processor 12 to prevent the processor 12 from reading data.
    [22] In the above-described embodiment, the first-in, first-out memory 14 is shown to be reset in response to a reset signal output from the processor 10, but is applied from a control unit (not shown) other than the processors 10 and 12. It can also be configured to reset in response to the reset signal (reset).
    [23] That is, the first-in, first-out memory 14 is provided between the two processors 10 and 12 in a manner as shown in FIG. 1 to enable data transfer between processors having different data rates.
    [24] FIG. 2 is a block diagram of the first-in first-out memory shown in FIG. 1, wherein the dual port memory cell array 20, the write pulse generation circuit 22, the write address generation circuit 24, the write data register 26, and the read pulse generation are shown. The circuit 28, the read address generation circuit 30, the read data register 32, and the flag generation circuit 34 are comprised.
    [25] The function of each of the blocks shown in FIG. 2 will be described below.
    [26] The dual port memory cell array 20 writes data in response to the write address WA and reads data in response to the read address RD. The write pulse generation circuit 22 generates the internal write clock signal iWCK in response to the inverted write enable signal WEB and the write clock signal WCK when the full flag signal Full is not generated. The write address generation circuit 24 is reset in response to the reset signal reset and generates the write address WA in response to the internal write clock signal iWCK. The write data register 26 stores the write data WD in response to the internal write clock signal iWCK and outputs the write data WD to the dual port memory cell array 20. The read pulse generation circuit 28 generates the internal read clock signal iRCK in response to the inverted read enable signal WEB and the read clock signal RCK when the empty flag signal Empty is not generated. The read address generation circuit 30 is reset in response to the reset signal reset, and generates the read address RA in response to the internal read clock signal iRCK. The read data register 32 outputs data output from the dual port memory cell array 20 as read data RD in response to the internal read clock signal iRCK. In response to the reset signal reset, the flag generation circuit 34 resets the full flag signal Full and the empty flag signal Empty, and compares the write address WA with the read address RA. The full flag signal Full is generated in response to the clock signal iWCK, and the empty flag signal Emmpty is generated in response to the internal read clock signal iRCK.
    [27] FIG. 3 is a circuit diagram showing the configuration of an embodiment of the dual port memory cell array shown in FIG. 2, wherein n write word lines wwl1, ..., wwln and m write bit line pairs ((wbl1, wbl1b)). , ..., (wblm, wblmb)), and n read word lines (rwl1, ..., rwln) and m read bit line pairs ((rbl1, rbl1b), ..., (rblm, rblmb)) is composed of m x n memory cells MC connected between each other.
    [28] Each of the memory cells MC includes NMOS transistors N1 and N2 for transmitting write data, NMOS transistors N3 and N4 for transmitting read data, and inverters I1 and I2 for latching data. It is comprised by the latch LA1 comprised of).
    [29] The functions of each of the memory cells MC shown in FIG. 3 will be described below.
    [30] The NMOS transistors N1 and N2 are write bit line pairs (wbl1, wbl1b), ..., (wbln, wblnb) in response to a signal transmitted to the write word lines wwl1, ..., wwlm. ) Is transmitted to the nodes n1 and n2, respectively. The NMOS transistors N3 and N4 read the data of the nodes n1 and n2 in response to the signal transmitted to the read word lines rwl1,..., Rwlm and the read bit line pairs (rbl1 and rbl1b). , ..., (rbln, rblnb)). The latch LA1 latches data of the nodes n1 and n2.
    [31] Fig. 4 is a circuit diagram of an embodiment of a conventional write address generating circuit, which comprises a column address generating circuit 40 composed of n bit serial cyclic shift registers WCA0 to WCA (n-1) for selecting n bit line pairs, and It consists of an m-bit serial cyclic shift register (WRA0 to WRA (m-1)) for selecting m word lines.
    [32] The n-bit serial circuit shift register (WCA0 to WCA (n-1)) is a master transfer and CMOS transfer consisting of a latch (LA2) consisting of a CMOS transfer gate (C1), an NMOS transistor (NM1), and inverters (I3, I4) A register WCA0 composed of a slave portion composed of a latch LA3 composed of a gate C2 and inverters I5 and I6, and a CMOS transfer gate C3, a PMOS transistor PM1 and inverters I7 and I8. Registers WCA1, ..., WCA (n-1) comprising a master portion composed of latch LA4 configured and a slave portion composed of latch LA5 composed of CMOS transfer gate C4 and inverters I9, I10. It consists of).
    [33] The m-bit serial iterative shift registers WRA0 to WRA (m-1) are the same as the registers WRA0 having the same configuration as the registers WCA0, and the registers WCA1, ..., WCA (n-1). It consists of registers WRA1 to WRA (m-1).
    [34] an inverter I11 for inverting the internal write clock signal iwck for controlling the CMOS transfer gates C1, C2, C3, and C4 of the n-bit serial circuit shift registers WCA0 to WCA (n-1), Control circuit 44 for generating a control signal for controlling the CMOS transfer gates C1, C2, C3, C4 of the m-bit serial circuit shift registers WRA0 to WRA (m-1), and the shift registers NMOS transistor NM1 of (WCA0 to WCA (n-1), WRA0 to WRA (m-1)), and inverter I12 for inverting the reset signal (reset) for controlling the PMOS transistor PM1. Consists of.
    [35] The operation of the circuit shown in Fig. 4 is as follows.
    [36] The PMOS transistors (PM1) and NMOS transistors (NM1) of the n-bit serial circuit shift registers (WCA0 to WCA (n-1)) and the m-bit serial circuit shift registers (WRA0 to WRA (m-1)) are at "high" levels. It is on when a reset signal of is applied. The latches LA2 and LA4 invert and latch the signals transmitted from the PMOS transistors PM1 and NMOS transistors NM1 to write master columns and row addresses (wmca0 to wmca (n-1), wmra0 to wmra (m-). 1)) generates "10 ... 0" respectively. The CMOS transfer gates C2 and C4 of the n-bit serial circuit shift registers WCA0 to WCA (n-1) turn on when the internal write clock signal iwck transitions from the "low" level to the "high" level. The write slave column addresses wsca (n-1) and wsca0 to wsca (n-2) are transmitted to the latches LA2 and LA4, respectively. Each of the latches LA2 and LA4 inverts and latches an output signal of the CMOS transfer gates C1 and C3 to generate the write master column addresses wmca0 to wmca (n-1). The CMOS transfer gates C1 and C3 are turned on when the internal write clock signal iwck transitions from the "high" level to the "low" level, latching the write master column addresses wmca0 to wmca (n-1). Transmit to LA3 and LA5, respectively. Each of the latches LA3 and LA5 inverts and latches an output signal of the CMOS transfer gates C2 and C4 to generate the write slave column addresses wsca0 to wsca (n-1).
    [37] That is, the n-bit serial cyclic shift registers WCA0 to WCA (n-1) reset the write master column addresses wmca0 to wmca (n-1) to "10 ... 0" in response to the reset signal. Then, each time the internal write clock signal iwck transitions from the "low" level to the "high" level, the write mast column address wmca0 to wmca (n-1) is shifted by one bit to "01 ... 0". 00 ... 1 ". As a result, the n-bit serial cyclic shift registers WCA0 to WCA (n-1) repeatedly perform the shifting operation from " 10 ... 0 " to " 00 ... 1 ".
    [38] The m-bit serial traversal shift registers WRA0 to WRA (m-1) perform the same operations as the n-bit serial traversal shift registers WCA0 to WCA (n-1). However, the m-bit serial circuit shift registers WRA0 to WRA (m-1) do not perform the shifting operation in response to the CMOS write gates C1, C2, C3, and C4 in response to the internal write clock signal iwck. The shifting operation is performed in response to the output signal of the control circuit 44. When the write slave column address wsca (n-1) is "1", the control circuit 44 does not perform the shifting operation because the output signal of the control circuit 44 becomes "0". The output signal of 44 becomes "1" and the shifting operation is performed. That is, the m-bit serial circuit shift registers WRA0 to WRA (m-1) perform a shifting operation when a carry is generated from the column address generation circuit 40, and do not perform a shifting operation when a carry is not generated.
    [39] The write master column addresses wmca0 to wmca (n-1) generated from the write address generation circuit shown in FIG. 4 are the write bit line pairs (wbl1, wbl1b), ... of the dual port memory cell array shown in FIG. ., (wbln, wblnb)) is used as a signal for selecting, and the write word lines wwl1,... of the dual port memory cell array shown in FIG. 3 by the write master row addresses wmra0 to wmra (m-1). .., wwlm) is used as a signal to select.
    [40] FIG. 5 is a circuit diagram of an embodiment of a conventional read address generating circuit, and is configured in the same manner as the write address generating circuit shown in FIG.
    [41] In Fig. 5, the column address generating circuit 40 shown in Fig. 4 is shown by 50, the row address generating circuit 42 is shown by 52, and the control circuit 44 is shown by 54. In Figs. The n bit shift registers WCA0 to WCA (n-1) are represented by RCA0 to RCA (n-1), and the m bit shift registers WRA0 to WRA (m-1) are represented by RRA0 to RRA (m-1). ). Also, the internal write clock signal iwck is an internal read clock signal irck, and the write master column and row addresses wmca0 to wmca (n-1) and wmra0 to wmra (m-1) are read master columns and row. Addresses rmrm0 to rmca (n-1) and rmra0 to rmra (m-1) are shown respectively.
    [42] Since the operation of the circuit shown in Fig. 5 operates in the same manner as the circuit shown in Fig. 4, it will be easily understood with reference to the operation description of the circuit shown in Fig.
    [43] The read master column addresses rmca0 to rmca (n-1) generated from the read address generation circuit shown in FIG. 5 are the read bit line pairs (rbl1, rbl1b), ... of the dual port memory cell array shown in FIG. ., (rbln, rblnb)) are used as signals for selecting, and the read word lines rwl1, .r of the dual port memory cell array shown in Fig. 3 by read master row addresses rmra0 to rmra (m-1). .., rwlm) is used as a signal to select.
    [44] 6 is a block diagram of an embodiment of a conventional flag generating circuit, which is composed of a comparing circuit 60 and a flag signal generating circuit 62. As shown in FIG.
    [45] The operation of each of the blocks shown in FIG. 6 will be described below.
    [46] The comparison circuit 60 includes write master column and row addresses wmca0 to wmca (n-1), wmra0 to wmra (m-1), and read master column and row addresses rmca0 to rmca (n-1) and rmra0 to rmra (m-1)) is compared and the control signal CO is generated when the comparison results match. The flag signal generation circuit 62 generates a full flag signal Full when the control signal CO is generated in response to the internal write clock signal iwck, and the control signal CO is applied to the internal read clock signal irck. In response, an empty flag signal (Empty) is generated.
    [47] Fig. 7 is a timing diagram for generating a full flag signal in the embodiment of a conventional flag generating circuit, in which an inverted write enable signal WEB (not shown) and a write clock signal WCK of "low" level are generated from the outside, The operation timing diagram when the inverted read enable signal REB (not shown) and the read clock signal RCK of the high " level are generated.
    [48] An internal write clock signal iwck is generated in response to the write clock signal WCK, and the write address WA is shifted in response to the internal write clock signal iwck, thereby shifting the last write address from the first write address wm0. up to (wm (k-1)), and again the first write address wm0. At this time, the read address rm0 and the write address wm0 become the same to generate the control signal CO, and the control signal CO is generated in response to the internal write clock signal iwck, thereby causing the full flag signal Full. Is generated.
    [49] However, since the flag generation circuit of the conventional first-in-first-out memory generates the full flag signal Full by comparing the current write address with the current read address, the full flag signal Full from the time when the write clock signal WCK is generated. There was a problem that the period (TFull) until the () occurs to be long.
    [50] Fig. 8 is an empty flag signal generation timing diagram of an embodiment of a conventional flag generation circuit, in which " low " level inverted write enable signal WEB and write clock signal WCK are generated, and " low " The operation timing diagram when the inverted read enable signal REB and the read clock signal RCK are generated, and the clock cycle of the read clock signal RCK is faster than the clock period of the write clock signal WCK.
    [51] An internal write clock signal iwck is generated in response to the write clock signal WCK, and a write address WA is generated in response to the internal write clock signal iwck. The internal read clock signal irck is generated in response to the read clock signal RCK, and the read address RA is generated in response to the internal read clock signal irck. By the way, when the write address wm (k-8) is generated, the control signal CO is generated when the read address wm (k-8) is generated. At this time, the control signal CO is generated as an empty flag signal Impty in response to the internal read clock signal irck.
    [52] However, the conventional flag generation circuit of the first-in-first-out memory generates an empty flag signal (Empty) by comparing the current write address with the current read address. Therefore, the empty flag signal (Empty) is generated from the time when the read clock signal RCK is generated. There was a problem in that the period until the occurrence of) becomes long.
    [53] That is, the conventional flag generation circuit of the first-in first-out memory has a problem that the timing of generating the flag signals is generated after the current write address or the current read address is generated, which is not suitable for a high speed system.
    [54] An object of the present invention is to provide a first-in, first-out memory suitable for a high speed system by advancing the timing of generation of flag signals.
    [55] Another object of the present invention is to provide a flag signal generating method of a first-in first-out memory for achieving the above object.
    [56] A first-in, first-out memory of the present invention for achieving the above object includes a write address generating means for generating a write address in response to a write clock signal, a read address generating means for generating a read address in response to the read clock signal, and a plurality of writes. And a plurality of memory cells between each of the read word lines and each of the plurality of write and read bit lines, store write data in response to the write address, and output read data in response to the read address. Comparing the memory cell array and the next write address with the current read address and generating a full flag signal in response to the write clock signal, and comparing the current write address with the next read address. In response to a signal And flag signal generating means for generating a tee flag signal.
    [57] A method of generating a flag signal of a first-in first-out memory of the present invention for achieving the above another object comprises a plurality of memory cells between each of a plurality of write and read word lines and a plurality of write and read bit lines, A method of generating a flag signal of a first-in first-out memory having a memory cell array for storing write data in response to the read data and outputting the read data in response to the read address, wherein the write address is generated in response to the write clock signal. Generating a read address in response to a clock signal, and comparing a next write address with a current read address to generate a full flag signal in response to the write clock signal, and generating a current write address and a next read address. Compare the leads if they are equal And generating an empty flag signal in response to the clock signal.
    [1] 1 is a block diagram illustrating data transfer between conventional processors.
    [2] FIG. 2 is a block diagram of the first-in, first-out memory shown in FIG.
    [3] FIG. 3 is a circuit diagram showing a configuration of an embodiment of the dual port memory cell array shown in FIG.
    [4] 4 is a circuit diagram of an embodiment of a conventional write address generating circuit.
    [5] 5 is a circuit diagram of an embodiment of a conventional read address generating circuit.
    [6] 6 is a block diagram of an embodiment of a conventional flag generating circuit.
    [7] Fig. 7 is a timing diagram of full flag signal generation in the embodiment of the conventional flag generation circuit.
    [8] 8 is an empty flag signal generation timing diagram of an embodiment of a conventional flag generation circuit.
    [9] 9 is a circuit diagram of an embodiment of a write address generating circuit of the present invention.
    [10] Fig. 10 is a circuit diagram of an embodiment of a read address generating circuit of the present invention.
    [11] Fig. 11A shows the full flag signal generation circuit of the embodiment of the present invention, and Fig. 11B shows the empty flag signal generation circuit of the embodiment.
    [12] Fig. 12 is a circuit diagram of a write address generating circuit of another embodiment of the present invention.
    [13] Fig. 13 is a circuit diagram of a read address generating circuit of another embodiment of the present invention.
    [14] Fig. 14A is a block diagram of a flag generating circuit of another embodiment of the present invention, and Fig. 14B shows an empty flag signal generating circuit of another embodiment.
    [15] Fig. 15 is a timing diagram of full flag signal generation in the embodiment of the flag generation circuit of the present invention.
    [16] Fig. 16 is an empty flag signal generation timing diagram of the embodiment of the flag generation circuit of the present invention.
    [58] Hereinafter, the first-in, first-out memory of the present invention will be described with reference to the accompanying drawings.
    [59] Fig. 9 is a circuit diagram of an embodiment of the write address generating circuit of the present invention, which is the same as the structure of the write address generating circuit shown in Fig. 4, and has the m-bit shift registers WRA0 to WRA (m−) of the write row address generating circuit 40. Figs. 1) The inverter I15 is added to the registers WRA0 constituting the 1), and the write row address generation circuit in which the inverter I16 is added to each of the registers WRA1, ..., WRA (m-1). It is different from 42.
    [60] Inverter I15 of register WRA0 inverts write slave row addresses wsra0, ... to generate addresses cwsra0, ..., and registers WRA1, ..., WRA (m-). 1)) Each inverter I16 inverts the write slave row addresses wsra1, ..., wsra (m-1), respectively, to generate the addresses cwsra1, ..., cwsra (m-1). . Inverters I15 and I16 pre-generate the next write master row address in the current state. That is, by adding inverters I15 and I16, the next write master row address is generated in the current state without changing the current row address.
    [61] Fig. 10 is a circuit diagram of an embodiment of the read address generating circuit of the present invention, which is the same as the structure of the read address generating circuit shown in Fig. 5, and has m-bit shift registers RRA0 to RRA (m−) of the read row address generating circuit 50. 1) The inverter I15 is added to the register RRA0 constituting the readout address, and the read row address generation circuit 52 in which the inverter I16 is added to the registers RRA1, ..., RRA (m-1). ') Is different.
    [62] Inverter I15 of register RRA0 inverts read slave row addresses rsra0, ... to generate addresses crsra0, ..., and registers RRA1, ..., RRA (m-). 1)) Each inverter I16 inverts the read slave row addresses rsra1, ..., rsra (m-1), respectively, to generate the addresses crsra1, ..., crsra (m-1). . Inverters I15 and I16 pre-generate the next read master row address in the current state. That is, by adding inverters I15 and I16, the next read master row address is generated in the current state without changing the current row address.
    [63] Fig. 11A shows the full flag signal generation circuit of the embodiment of the present invention, and Fig. 11B shows the empty flag signal generation circuit of the embodiment.
    [64] The full flag signal generation circuit is composed of a comparison circuit 70 and a flip-flop 72, and the empty flag signal generation circuit is composed of a comparison circuit 74 and a flip-flop 76.
    [65] The operation of the circuit shown in Fig. 11A will be described below.
    [66] When the write slave column address wsca (n-1) is "1", the comparison circuit 70 writes the write master row and column addresses wmra0, wmra (m-1) to wmra1, wmca0, wmca (n-1). ) to wmca1) and read row and column addresses (rmra (m-1) to rmra0, rmcan to rmca1), respectively, and if the write slave column address (wsca (n-1)) is "0", write low And the column addresses (cwsra (m-1) to cwsra0, wmca0, wmca (n-1) to wmca1) and read row and column addresses (rmra (m-1) to rmra0, rmca (n-1) to rmca1). When the comparison results match, the control signal WCO is generated. The flip-flop 72 latches the control signal WCO in response to the internal write clock signal iwck to generate a full flag signal Full.
    [67] The operation of the circuit shown in Fig. 11B is as follows.
    [68] When the read slave column address rsca (n-1) is "1", the comparison circuit 74 writes the write master row and column addresses wmra (m-1) to wmra0, wmca (n-1) to wmca1). And the read row and column addresses rmra0, rmra (m-1) to rmra1, rmca0, rmca (n-1) to rmca1, respectively, and the read slave column address rsca (n-1) is " 0 " Is the write row and column address (wmra (m-1) to wmra0, wmca (n-1) to wmca0) and the read row and column address (crsra (m-1) to crsra0, rmca0, rmca (n-1). ) and rmca1) are compared, and if the comparison result is identical, the control signal RCO is generated. The flip-flop 76 latches the control signal RCO in response to the internal read clock signal irck to generate an empty flag signal Impty.
    [69] That is, the flag signal generation circuit of the first-in first-out memory of the present invention compares the next write master row and column address with the current read master row and column address in order to generate a full flag signal (Full), and empty flag signal (Empty). Compares the next read master row and column address with the current write master row and column address.
    [70] Therefore, the flag signal generation circuit of the first-in first-out memory of the present invention can advance the generation time of the flag signals.
    [71] By the way, the write and read address generation circuits of the present invention shown in Figs. 9 and 10 require a shift register in which as many registers as the number of word lines and bit line pairs are connected in series, which complicates the circuit configuration.
    [72] Fig. 12 is a circuit diagram of a write address generating circuit according to another embodiment of the present invention, in which the column address generating circuit 40 composed of n bit serial circulation shift registers WCA0 to WCAn and (my) bit serial circulation shift registers WRA10 to WRA1. row address generation circuit, control circuits 84 and 86, and inverters I11 composed of (my-1)) 80 and y-bit serial cyclic shift registers (WRA00 to WRA0 (y-1)) 82. , I12).
    [73] The configuration of the column address generating circuit 40 is the same as that of the column address generating circuit 40 shown in FIG.
    [74] The (my) bit serial circulation shift register (WRA00 to WRA0 (my-1)) (80) serially connects and configures my registers constituting the m bit serial shift register shown in FIG. (WRA10 to WRA1 (y-1)) 82 is configured by serially connecting y registers constituting the m-bit serial shift register shown in FIG.
    [75] The control circuit 84 is configured in the same manner as the control circuit 44 shown in Fig. 9, and the control circuit 86 is divided into inverters I17, I18, and I19, and AND gates AND2 and AND3. Consists of.
    [76] The operation of the circuit shown in Fig. 12 is as follows.
    [77] The n-bit serial circuit shift registers WCA0 to WCA (n-1) are reset in response to the reset signal reset, and perform a shifting operation in response to the internal write clock signal iwck. That is, it operates in the same manner as the n-bit serial cyclic shift registers WCA0 to WCA (n-1) shown in FIG.
    [78] The (m-y) bit serial cyclic shift registers WRA00 to WRA0 (m-y-1) are reset in response to the reset signal reset, and perform a shifting operation in response to the output signal of the control circuit 84. That is, the (m-y) bit serial cyclic shift registers WRA00 to WRA0 (m-y-1) perform a shifting operation when a carry is generated from the n-bit serial cyclic shift registers WCA0 to WCA (n-1). That is, it operates in the same manner as the m-bit serial cyclic shift registers WRA0 to WRA (m-1) shown in FIG.
    [79] Then, the y-bit serial cyclic shift registers WRA10 to WRA1 (y-1) are reset in response to the reset signal reset, and perform a shifting operation in response to the output signal of the control circuit 86. That is, the y-bit serial circulation shift registers (WRA10 to WRA1 (y-1)) are the n-bit serial circulation shift registers (WCA0 to WCA (n-1)) and the (my) bit serial circulation shift registers (WRA00 to WRA-0). When carry is generated from (my-1)), the shifting operation is performed.
    [80] Inverters I17 and I18 of the control circuit 86 are write slave column addresses wsca (n-1) and (my) bits generated from the n-bit serial circuit shift registers WCA0 to WCA (n-1). The carry is detected by inverting the write slave row address wsra0 (my-1) generated from the serial cyclic shift registers WRA00 to WRA0 (my-1). The AND gate AND2 ANDs the output signals of the inverters I17 and I18, and the AND gate AND3 ANDs the AND gate AND2 and the internal write clock signal iwck. Thus, CMOS transfer gates of the y-bit serial cyclic shift registers WRA10 to WRA1 (y-1) using a signal inverted by the inverter I19 by the output signals of the AND gate AND3 and the AND gate AND3. (C1, C2, C3, C4) is controlled.
    [81] The shift register shown in Fig. 12 is configured by dividing the m-bit serial shift register into an (m-y) bit serial shift register and a y-bit serial shift register, thereby reducing the number of registers constituting the serial shift register, thereby simplifying the circuit configuration.
    [82] Fig. 13 is a circuit diagram of a read address generation circuit of another embodiment of the present invention, in which the column address generation circuit 50 composed of n-bit serial cyclic shift registers RCA0 to RCAn, and (my) bit serial cyclic shift registers RRA10 to A row address generation circuit, control circuits 94 and 96, and inverters (RRA1 (my-1)) 90 and a y-bit serial circuit shift register (RRA00 to RRA0 (y-1)) 92. I11 and I12).
    [83] The configuration of the column address generation circuit 50 is the same as that of the column address generation circuit 50 shown in FIG.
    [84] The (my) bit serial circulation shift register (RRA00 to RRA0 (my-1)) 90 connects and configures my registers constituting the m bit serial shift register shown in FIG. (RRA10 to RRA1 (y-1)) 92 is configured by serially connecting y registers constituting the m-bit serial shift register shown in FIG.
    [85] The configuration of the control circuits 94 and 96 is the same as that of the control circuits 84 and 86 shown in Fig. 12, only the input signal is different.
    [86] The operation of the circuit shown in FIG. 13 will be readily understood with reference to the operation description of the circuit shown in FIG.
    [87] In the above-described embodiment, the row address generation circuit is divided into two shift registers. However, the row address and column address generation circuits may be separated into two or more shift registers.
    [88] Fig. 14A is a block diagram of a flag generating circuit of another embodiment of the present invention, and Fig. 14B shows an empty flag signal generating circuit of another embodiment.
    [89] The full flag signal generation circuit is composed of a comparison circuit 100 and a flip-flop 102, and the empty flag signal generation circuit is composed of a comparison circuit 104 and a flip-flop 106.
    [90] The operation of the circuit shown in Fig. 14A will be described below.
    [91] When the write slave column address wsca (n-1) is "1", the comparison circuit 100 write-write master row and column addresses wmra10, wmra (y-1) to wmra11, wmra00, wmra0 (my-1). ) to wmra01, wmca0, wmca (n-1) to wmca1) and read row and column addresses (rmra1 (y-1) to rmra10, rmra (my-1) to rmra0, rmcan to rmca1), respectively. If the slave column address (wsca (n-1)) is "0", the write row and column address (cwsra (y-1) to cwsra0, cwsra (my-1) to cswra0, wmca0, wmca (n-1) wmca1) and the read row and column addresses rmra1 (y-1) to rmra10, rmra (my-1) to rmra0, and rmcan to rmca1 are compared to each other to generate a control signal WCO. The flip-flop 102 latches the control signal WCO in response to the internal write clock signal iwck to generate a full flag signal Full.
    [92] The operation of the circuit shown in Fig. 14B is as follows.
    [93] When the read slave column address rscan is "1", the comparison circuit 104 writes the write master row and column addresses wmra1 (y-1) to wmra10, wmca0 (my-1) to wmca00, and wmca (n-1). ) to wmca0) and read row and column addresses (rmra10, rmra1 (y-1) to rmra11, rmca00, rmca0 (my-1) to rmca01, rmra0, rmra (n-1) to rmra1), respectively. If the slave column address rsca (n-1) is "0", the write row and column address (cwsra10, cwsra1 (y-1) to cwsra11, cwsra00, cwsra0 (y-1) to cwsca01, wmca (n-). 1) Comparing the ~ wmca0) with the read row and column addresses rmca0 and rmca (n-1) to rmca1, the control signal RCO is generated when the comparison results match. The flip-flop 106 latches the control signal RCO in response to the internal read clock signal irck to generate an empty flag signal Impty.
    [94] That is, the flag signal generation circuit of the first-in first-out memory of the present invention compares the next write master row and column address with the current read master row and column address in order to generate a full flag signal (Full), and empty flag signal (Empty). Compares the next read master row and column address with the current write master row and column address.
    [95] Fig. 15 is a timing diagram of generating a full flag signal according to the embodiment of the flag generating circuit of the present invention. The inverted write enable signal WEB (not shown) and the write clock signal WCK of the "low" level are externally generated. The operation timing diagram when the inverted read enable signal REB (not shown) and the read clock signal RCK of the "high" level are generated.
    [96] That is, when the last write address wm (k-1) is generated by the method as shown in the timing diagram of FIG. The first write address wm0 and the read address rm0 are compared with each other to generate the control signal WCO. The full flag signal Full latches and outputs the control signal WCO in response to the internal write clock signal iwck.
    [97] Therefore, the full flag signal generation circuit of the first-in first-out memory of the present invention reduces the period TFull from the time when the write clock signal WCK is generated until the full flag signal Full is generated.
    [98] Fig. 16 is an empty flag signal generation timing diagram of an embodiment of the flag generation circuit of the present invention, in which an inverse write enable signal WEB (not shown) and a write clock signal WCK of " low " level are generated from outside; A low-level inverted read enable signal REB (not shown) and a read clock signal RCK are generated, and the clock cycle of the read clock signal RCK is faster than the clock period of the write clock signal WCK. The operation timing diagram in the case.
    [99] When the write address wm (k-8) is generated in the manner as shown in the timing diagram of Fig. 8, at this time, the current write address wm (k-8) and the current read address wm (k-9) are generated. ) Is not compared, but the read address wm (k-8) to be generated next is compared to generate the control signal RCO. The empty flag signal Empty latches and outputs the control signal RCO in response to the internal read clock signal irck.
    [100] Therefore, the empty flag signal generation circuit of the first-in first-out memory of the present invention reduces the period TEmpty from when the read clock signal RCK is generated until the empty flag signal Emmpty is generated.
    [101] Therefore, the flag signal generation circuit of the first-in first-out memory of the present invention generates a full flag signal by comparing the next write address with the current read address, and the empty flag signal by comparing the current write address with the next read address. By generating, it is possible to advance the generation time of the flag signal.
    [102] In the above-described embodiment, the circuit for generating the write address and the read address is constituted by the shift register, but it is possible to apply the method of the present invention even when the counter is used.
    [103] Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.
    [104] Therefore, the first-in first-out memory of the present invention and the flag signal generating method thereof can be easily applied to a high speed system because the flag signal is generated at a high speed.
    权利要求:
    Claims (13)
    [1" claim-type="Currently amended] Write address generating means for generating a write address in response to the write clock signal;
    Read address generating means for generating a read address in response to the read clock signal;
    And a plurality of memory cells between each of the plurality of write and read word lines and each of the plurality of write and read bit lines, store write data in response to the write address, and read data in response to the read address. A memory cell array for output; And
    The next write address is compared with the current read address, and if it is the same, a full flag signal is generated in response to the write clock signal, and if the current write address is compared with the next read address, it is empty in response to the read clock signal. A first in, first out memory comprising flag signal generating means for generating a flag signal.
    [2" claim-type="Currently amended] The method of claim 1, wherein the write address generating means
    Write column address generating means for generating a write column address for selecting the plurality of write bit lines; And
    And a write row address generating means for generating a write row address for selecting the plurality of write word lines.
    [3" claim-type="Currently amended] The method of claim 2, wherein the write column address generating means
    At least one or more predetermined serial serial first shift registers for generating the write column address;
    The serial bit first shift register of the predetermined bit resets the write column address in response to a reset signal, generates a write master column address in response to a rising transition of the write clock signal, and generates a write master column address in the falling transition of the write clock signal. And a write slave column address in response.
    [4" claim-type="Currently amended] The method of claim 2, wherein the write row address generating means
    At least one or more predetermined bit serial serial second shift registers for generating said write row address;
    The second serial register of the predetermined bit resets the write row address in response to the reset signal, and writes the write master row address in response to the rising transition of the write clock signal when a carry is generated from the write column address generating means. And a write slave row address and a next write row address in response to the falling transition of the write clock signal.
    [5" claim-type="Currently amended] The write column address generating means according to claim 2, wherein the write column address generating means comprises a predetermined number of predetermined bit serial serial first shift registers.
    Each of the predetermined number of serial traversal first shift registers
    The write column address is reset in response to the reset signal, and if a carry is generated from the serial cycle shift registers for generating a lower bit among the predetermined number of serial cycle shift registers, And a write master column address and a write slave column address and a next write slave column address in response to the falling transition of the write clock signal.
    [6" claim-type="Currently amended] 3. The method of claim 2, wherein the write row address generating means is constituted by a predetermined number of predetermined number of bit serial serial shift second registers.
    Each of the predetermined number of serial traversing second shift registers
    The write clock is reset in response to the reset signal, when a carry is generated from the serial column shift registers for generating a lower bit among the write column address generating means and the predetermined number of serial circuit shift registers. And a write master row address in response to a rising transition of the signal, and a write slave row address and a next write row address in response to the falling transition of the write clock signal.
    [7" claim-type="Currently amended] The method of claim 1, wherein the read address generating means
    Read column address generating means for generating a read column address for selecting the plurality of read bit lines; And
    And first read row address generating means for generating a read row address for selecting the plurality of read word lines.
    [8" claim-type="Currently amended] The method of claim 7, wherein the read column address generating means
    At least one or more predetermined bit serial traversing third shift registers for generating the read column address;
    The serial bit third shift register of the predetermined bit resets the read column address in response to a reset signal, generates a read master column address in response to a rising transition of the read clock signal, and generates a read master column address in a falling transition of the read clock signal. And a read slave column address in response.
    [9" claim-type="Currently amended] The method of claim 7, wherein the read row address generating means
    At least one or more predetermined bit serially sequential shift registers for generating the read row addresses;
    The fourth serial bit register of the predetermined bit resets the read row address in response to the reset signal, and if a carry is generated from the read column address generating means, the read master row address in response to the rising transition of the read clock signal. And a read slave row address and a next read row address in response to the falling transition of the read clock signal.
    [10" claim-type="Currently amended] 8. The method according to claim 7, wherein the write column address generating means is constituted of a predetermined number of predetermined bit serial serial third shift registers.
    Each of the predetermined number of serial traversing third shift registers
    The write column address is reset in response to the reset signal, and if a carry is generated from the serial cycle shift registers for generating a lower bit among the predetermined number of serial cycle shift registers, And a write master column address and a write slave column address and a next write slave column address in response to the falling transition of the write clock signal.
    [11" claim-type="Currently amended] 8. The method of claim 7, wherein the write row address generating means comprises a predetermined number of predetermined bit serial serial shift second registers.
    Each of the predetermined number of serial traversing fourth shift registers
    The write clock is reset in response to the reset signal, when a carry is generated from the serial column shift registers for generating a lower bit among the write column address generating means and the predetermined number of serial circuit shift registers. And a write master row address in response to a rising transition of the signal, and a write slave row address and a next write row address in response to the falling transition of the write clock signal.
    [12" claim-type="Currently amended] The method of claim 1, wherein the flag signal generating means
    A first comparison section configured to generate a first comparison agreement signal by comparing the next write address with the current read address and equalizing the first write address;
    A first flip-flop for generating the full flag signal by inputting the first comparison coincidence signal in response to the write clock signal;
    A second comparison channel configured to compare the current write address with a next read address and generate a second comparison agreement signal if they are identical; And
    And a second flip-flop for inputting the second comparison coincidence signal in response to the read clock signal to generate the empty flag signal.
    [13" claim-type="Currently amended] Having a plurality of memory cells between each of a plurality of write and read word lines and a plurality of write and read bit lines, storing write data in response to a write address, and outputting read data in response to the read address A flag signal generation method of a first-in, first-out memory having a memory cell array for
    Generating a write address in response to the write clock signal, and generating a read address in response to the read clock signal; And
    The next write address is compared with the current read address, and if it is the same, a full flag signal is generated in response to the write clock signal. Generating a flag signal; and a flag signal generating method of a first-in first-out memory.
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    同族专利:
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    US6463000B2|2002-10-08|
    US20020080672A1|2002-06-27|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-12-26|Application filed by 윤종용, 삼성전자 주식회사
    2000-12-26|Priority to KR1020000082094A
    2002-07-04|Publication of KR20020052669A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000082094A|KR20020052669A|2000-12-26|2000-12-26|First-In First-OUT memory and flag signal generating method thereof|
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